TRANSISTOR GATING: A Technique for Leakage Power Reduction in CMOS Circuits

Abstract — In CMOS circuit’s design, as the threshold voltage is reduced due to voltage scaling, it leads to increase in sub-threshold leakage current and hence static power dissipation. In this paper we propose a power reduction technique named transistor gating. In this technique two sleep transistors PMOS and NMOS are inserted in between the supply voltage and ground. A PMOS is inserted in between pull-up network and network output and a NMOS is inserted in between pull-down network and ground. During standby mode both sleep transistor are turned off thereby increasing the resistance of the path from Vdd to ground, so that significant reduction in static power is achieved with increase in delay. This technique is tested on one bit full adder circuit. Design and simulation were done on cadence virtuoso and spectre tools using UMC 180nm process technology.